The analog circuit in a system LSI is increasing in importance. In order to realize the analog circuit in a CMOS process, countermeasures against variations in transistor manufacture during the manufacturing processes of semiconductors and the variations in transistor characteristics dependent on the ambient temperature during operation are a significant challenge. For instance, the drain current Id and the transconductance gm of a transistor vary due to dispersion of the oxide film thickness during manufacturing processes and in the width of polysilicon or the like even when the same driving voltage is given, and vary due to ambient temperatures. Due to these variations, problems arise from variations in operating speed or current consumption of analog circuits.
Japanese Patent Application Laid-Open No. Sho 61-114319 describes an MOS analog integrated circuit including n-pieces (plural) analog circuit blocks; n-pieces (plural) bias circuit blocks supplying biases corresponding with the n-pieces analog circuit blocks while receiving a common controlling signal; and a control circuit outputting the common controlling signal to the n-pieces bias circuit blocks.
Japanese Patent Application Laid-Open No. Hei 8-321584 describes a semiconductor integrated circuit having a differential amplifier that receives an internal signal center voltage into one of input terminals as a reference voltage, because when the threshold value of a MOSFET composing a circuit varies due to variations during the manufacture or variations in ambient temperature, the internal signal center voltage also varies in the same fashion.
Japanese Patent Application Laid-Open No. 2003-150258 describes a bias voltage generation circuit, which supplies a bias voltage at low power supply voltage and in a wide-power supply voltage range, and is able to realize reduction in consumption power and to reduce the influence of variations in manufacturing process and variations in temperature conditions during the operation.